Prof. Dr.-Ing. Michael Hübner

  • Professor/in - Lehrstuhl Eingebettete Systeme der Informationstechnik
Hübner, Michael

Adresse

Ruhr-Uni­ver­si­tät Bo­chum
Lehr­stuhl für Ein­ge­bet­te­te Sys­te­me der In­for­ma­ti­ons­tech­nik
Uni­ver­si­täts­stras­se 150
44780 Bo­chum

Raum
ID 1/341
Telefon:
(+49)(0)234 / 32 - 25975
Fax:
(+49)(0)234 / 32 - 14499
E-Mail:
michael.huebner@rub.de

Lebenslauf


Prof. Michael Hübner hat 2007 an der Universität Karlsruhe (TH) promoviert und am Karlsruher Institut für Technologie (KIT) im Jahre 2011 habilitiert. Michael Hübner arbeitet seit einem Jahrzehnt im Bereich rekonfigurierbarer Hardware, neuartiger Multicore-Architekturen und Anwendungsspezifischen Prozessoren. Dabei verwendet er neuartige Ansätze für den HW / SW Codesign mit dem Ziel, die Recheneffizienz der neuartigen Rechensysteme zur Entwurfs- und Laufzeit zu erhöhen. Michael Hübner ist Mit-Initiator von 7 erfolgreichen DFG Projekten, 7 EU Projekten und über 4 vom BMBF geförderten Projekte welche an der Universität Karlsruhe (TH) bzw. dem Karlsruher Institut für Technologie (KIT)beantragt wurden. Des Weiteren führt Prof. Hübner zahlreiche Kooperationen mit der Industrie. Dr. Hübner ist Haupt- und Co-Autor von über 150 internationalen wissenschaftlichen Veröffentlichungen. Michael Hübner ist Organisator zahlreicher internationaler Workshops, Konferenzen und Symposien und gleichzeitig Fachgutachter in international relevanten Fachjournalen und Konferenzen.


Forschung


Eingeladene Vorträge

  • „Dynamic and partial reconfiguration“, University of Brasilia, Brasil (September 2004)
  • „Exploitation of Run-Time Reconfiguration in Embedded System Applications”, Xilinx Labs, Dublin, Ireland (Februar 2006)
  • „Run-Time adaptive System Design“, University of Pisa, Italy (März 2006)
  • „Models and Tools for the Dynamic Reconfiguration of FPGAs“, FGAN Ettlingen, Germany (April 2006)
  • „Physical 2D Morphware and Power Reduction Methods for Everyone“, Dagstuhl Seminar, Germany (April 2006)
  • “Dynamic and Partial Reconfiguration for Adaptive Embedded Electronic Systems”, Univ. of York, United Kingdom (Januar 2007)
  • „Reconfigurable FPGAs for USCT", Karlsruhe, Germany (April 2009)
  • „Reconfigurable Computing“, EMICRO 2010, Porto Alegre, Brazil, (Mai 2010)
  • „Challenges and Visions in Reconfigurable Computing“, Univ. of Paris, France (Juni 2010)
  • „Novel adaptive System Design Methodologies“, Universität Bremen, Germany (November 2010)
  • „Advanced Application of dynamic and partial Reconfiguration“, University of Tallinn, Estland (Oktober 2011)
  • „Novel Trends in Adaptive Processor Design“, FETCH 2012, Alpes de Huiz, France (Januar 2012)
  • „Dynamic paramterizaion and manipulation of hardware“, PARMA 2012 workshop, Munich, Germany (Februar 2012)

Organisation von Konferenzen und Workshops

  • Co-Organizer des Workshop „Dynamic and partial reconfiguration of Virtex-II FPGAs“, International Conference on Field-Programmable Logic, (FPL) 2004
  • Co-Organisator des Friday Workshop „Future Trends in Automotive Electronics and Tool Integration“, Design, Automation and Test in Europe (DATE), 2006
  • Co-Organisator des Friday Workshop „FPGAs and Reconfigurable Systems: Adaptive Heterogeneous Systems-on-Chip and European Dimensions“, Design, Automation and Test in Europe (DATE), 2007
  • Co-Organizer des Tutorials „Reconfigurable Computing: Architectures, Tools and Applications“, Design, Automation and Test in Europe (DATE), 2007
  • Co-Organizer des Friday Workshop: „Reconfigurable Hardware: Emerging Trade-Offs through Granularity, Heterogeneity and Mixed-Signal Capability in Actual and Future Architectures“, Design, Automation and Test in Europe (DATE), 2008
  • Co-Organizer des Tutorial „Automotive Electronic Systems – Architectures, Tools, and Standardization“, Design, Automation and Test in Europe (DATE), 2008
  • Co-Organizer des Tutorial „Power Optimised Design Techniques for Modern FPGAs“, Design Automation and Test in Europe (DATE) 2009
  • Organisator des Workshop „System-On-Chip: Current Trends and the Future“, Design automation conference (DAC), 2009
  • Co-Organizer des Friday Workshop „Reconfigurable Computing: Lessons Learned, New Perspectives and Innovations“, Design Automation and Test in Europe (DATE), 2010
  • Co-Organizer des Friday Workshop „Designing for Embedded Parallel Computing Platforms: Architectures,Design Tools, and Applications“, Design Automation and Test in Europe (DATE) 2010
  • Organisator des Workshop „Multiprocessor System-On-Chip (MPSOC): Programmability, Run-Time Support and Hardware Platforms for High Performance Applications“, Design Automation Conference (DAC), 2010
  • Organizer des Workshop „Multiprocessor System on Chip for Cyber Physical Systems: Programmability, Run-Time Support and Hardware Platforms for High Performance Embedded Applications“, Design Automation Conference (DAC), 2011
  • Organisator des DAC Workshops on Industrial Automation, Design Automation Conference (DAC), 2012
  • General Chair INDIN 2013, Bochum, Germany
  • PhD Forum Chair of the ISVLSI 2014, Tampa Florida, USA
  • Program Co-Cahir of the AHS 2014, Leicester, UK
  • Program Co-Cahir of the FPL2014, Munich, Germany
  • Program Co-Chair of the ReconFig 2014, Cancun, Mexico
  • General Chair of the ISVLSI 2017, Bochum, Germany

Workshop und Konferenzleitung

  • Local Chair des IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006)
  • Program Chair des International Workshop on Reconfigurable Computing Education (RC-Education), 2007 (http://helios.informatik.uni-kl.de/RCeducation07/)
  • Program Chair des Reconfigurable Co-Centric SoCs Workshops (ReCoSoC) 2008 (http://www-eel.upc.edu/recosoc/)
  • Program Chair des International Workshop on Reconfigurable Computing Education (RC-Education), 2008 (http://helios.informatik.uni-kl.de/RCeducation08/)
  • Publicity Chair der International Conference on Reconfigurable Computing and FPGAs (RECONFIG), 2008 (http://www.reconfig.org/)
  • Sponsor and Exhibition Co-Chair der International Conference on Field-Programmable Logic, Reconfigurable Computing and Applications (FPL) 2009
  • Program Chair des Reconfigurable Co-Centric SoCs Workshops (ReCoSoC) 2010 (www.lirmm.fr/recosoc2010/)
  • Steering Commitee Member IEEE Computer Society Annual Symposium on VLSI (seit 2010)
  • Program Chair der Conference on Design and Architectures for Signal and Image Processing (DASIP), 2011
  • Program Co-Chair des Reconfigurable Architecture Workshop (RAW), 2012
  • Program Co-Chair des Symposium on Integrated Circuits and Systems Design (SBCCI), 2012
  • General Co-Chair der Conference on Design and Architectures for Signal and Image Processing (DASIP) 2012 in Karlsruhe

Mitgliedschaft in Programmkomitees

  • The International Conference on Field-Programmable Logic (FPL)
  • Symposium on Integrated Circuits and Systems Design (SBCCI)
  • IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
  • Reconfigurable Architecture Workshop (RAW)
  • Reconfigurable Co-Centric SoCs (ReCoSoc)
  • HiPEACRC stands for High Performance Embedded Architecture and Compilation Reconfigurable Computing Cluster (HiPEACRC)
  • IET Irish Signals and Systems Conference
  • International Conference on Field-Programmable Technology (FPT)
  • Design, Automation and Test in Europe (2005 bis 2009)
  • Design and Architectures for Signal and Image Processing (DASIP)

Projekte


DFG

  • Erfolgreiche Folgebeantragung des Forschungsprojektes ALadyn innerhalb des DFG Schwerpunktprogramms 1148 „Rekonfigurierbare Rechensysteme“ 2005
  • Beteiligung an der Antragsstellung des DFG Graduiertenkolleg 1194 „Selbstorganisierende Sensor Aktor Netzwerke“, 2005
  • Erfolgreiche Folgebeantragung des Forschungsprojektes ALadyn innerhalb des DFG Schwerpunktprogramms 1148 „Rekonfigurierbare Rechensysteme“ 2007
  • Erfolgreiche Wiederbeantragung der DFG geförderten Kooperation mit der Universität Brasilia, Thema „High Performance Computing“, Laufzeit 2007-2010
  • Beteiligung an der Wiederbeantragung des DFG Forschungsprojekts „Digital on Demand Organism (DodOrg)“, Laufzeit 2009 – 2011
  • Erfolgreiche Beantragung des Teilprojekts B1 “Rekonfigurierbare Mikroarchitekturen“ innerhalb des SFB / Transregio TRR89 „InvasIC“, eine E13 Stelle, Sachmittel, Laufzeit Mai 2010 – April 2014, Evaluation 2013
  • Erfolgreiche Beantragung des DFG Einzelantrags „Beschleunigung bildgebender Verfahren durch Einsatz von rekonfigurierbaren Hardwareplattformen am Beispiel der 3D Ultraschall-Computertomographie“, 3 E13 Stellen, Mittel für Hiwi, Sachmittel, Laufzeit 2 Jahre, Start April 2011

EU-Projekte

  • Maßgebliche Beteiligung am Projektantrag „AETHER“, Future Emerging Technology (FET) Projekt der EU, FP6, Laufzeit 2006-2009, (www.aether.ist.org)
  • Maßgebliche Beteiligung am Projektantrag „MORHEUS: Multi-purpOse dynamically Reconfigurable Platform for intensive HEterogeneoUS processing“, Integrated Project (IP) der EU, FP6, Laufzeit 2006-2009, (www.morpheus-ist.org)
  • Maßgebliche Beteiligung an der Beantragung des EU Projekts „REFLECT: Rendering FPGAs to Multi-Core Embedded Computing“, Small or medium-scale focused research project (STREP) proposal, FP7, Laufzeit 2010-2012
  • Maßgebliche Beteiligung an der Beantragung des EU Projekts „ACCORDANCE: A converged copper-optical-radio OFDMA-based access network with high capacity and flexibility“, Small or medium-scale focused research project (STREP) proposal, FP7, Laufzeit 2010-2012
  • Erfolgreiche Beantragung des EU Projekts „ALMA: Architecture oriented parallelization for high performance embedded Multicore systems using scilab“, Small or medium-scale focused research project (STREP) proposal, FP7, Laufzeit 2011-2014, Start September 2011 (Koordinator)
  • Erfolgreiche Beantragung des EU Projekts „FlexTiles: Self adaptive heterogeneous manycore based on Flexible Tiles“, Small or medium-scale focused research project (STREP) proposal, FP7, Laufzeit 2011-2014, Start Oktober 2011
  • Erfolgreiche Beantragung des EU Projekt “ARMOR: Advanced multi-parametric Monitoring and analysis for diagnosis and Optimal management of epilepsy and Related brain disorders”, Small or medium-scale focused research project (STREP) proposal, FP7, Laufzeit 2011-2014, Start Oktober 2011

BMBF, AIF

  • Beteiligung an der Antragstellung des BMBF Projekts „HERKULES“, Thema „Formale Verifikation von automobilspezifischen Protokollen“, Partner von Bosch, Laufzeit 2006-2009
  • Antragstellung des KIT Teilprojekts innerhalb des BMBF Projekt „Condor: Converged Heterogeneous Metro/Access Infrastructure“, Laufzeit April 2010- März 2013, Teilbereich: „Signal Processing“
  • Erfolgreiche Beantragung des vom AIF geförderten ZIM Projekts „JTAG basierende Qualitätsprüfung von Baugruppen“, Laufzeit 2010-2011
  • Erfolgreiche Beantragung des vom AIF geförderten ZIM Projekts „Monitoring von PCIExpress basierenden Systemen“, Laufzeit 2010-2011

DAAD

  • Erfolgreiche Beantragung und Wiederbeantragung der DAAD geförderten Kooperation mit der Universität Montpellier, Thema „Multiprocessor System on Chip“, Laufzeit 2007-2010
  • Erfolgreiche Neubeantragung der DAAD geförderten Kooperation mit der Universität Porto Alegre, Thema „Dependable Computing Architectures“, Laufzeit 2010-2011
  • Erfolgreiche Neubeantragung der DAAD geförderten Kooperation mit der Universität Porto, Portugal, Thema: „Heterogeneous Mutlicorearchitecture for High Performance Applications“, Laufzeit 2010-2011
  • Erfolgreiche Neubeantragung der DAAD geförderten Kooperation mit der Universität von Athen, Griechenland, Thema: „Virtualisierung heterogener Multiprozessorsysteme“

Industriekooperationen

  • Seit 2003: Einzelaufträge von Daimler in den Bereichen „Rekonfigurierbare Hardware im Automobil“
  • Vertragsausarbeitung für Forschungskooperation mit Endress und Hauser „Low Power FPGA in der Messtechnik“, Laufzeit 2008-2011, Bilaterales Industrieprojekt
  • Vertragsausarbeitung für Forschungskooperation mit dem Forschungszentrum Optronik und Mustererkennung (jetzt Fraunhofer IOSB): „Rekonfigurierbare Bildverarbeitungsfilter“, Laufzeit 2008-2009, bilaterale Forschungskooperation
  • Vertragsausarbeitung für Forschungskooperation mit Alcatel-Lucent: „Digitale Elektronik in der optischen Nachrichtenübertragung“, Laufzeit 2008-2009, bilaterales Industrieprojekt
  • Erfolgreiche Bewerbung bei Intel um einen Sigle Chip Cloud Computer. Der Computer steht seit September 2010 für 3 Jahre zur Verfügung
  • Forschungskooperation mit dem Fraunhofer IOSB, Thema: „Virtualisierungskonzepte für heterogene Multicore Architekturen“, Start Mai 2011, Laufzeit 8 Monate
  • Forschungskooperation mit der Firma MSC: „Muticoretechnologien für Low-Power Energy Metering“

KIT Exzellenzmittel

  • Erfolgreiche Beantragung eines Start-Up Budget aus den Exzellenzmitteln des KIT: „Rekonfigurierbare Hardware zur Beschleunigung der Bildrekonstruktion bei der Ultraschall Computer Tomographie“, gemeinsam mit dem IPE, Prof. Gemmeke, Campus Nord, Laufzeit 2008-2009
  • Mitantragsteller und Mitgründer der New Field Group „Design and computing in the nano era“ (Interne Ausschreibung des KIT), Prof. Mehdi Tahoori, 2009
  • Erfolgreiche Beantragung eines Start-Up Budget aus den Exzellenzmitteln des KIT: „Rekonfigurierbare Hardware für autonome Fluggeräte“, gemeinsam mit dem ITE, Prof. Trommer, Campus Nord, Laufzeit 2008-2009
  • Erfolgreiche Beantragung eines Start-Up Budget aus den Exzellenzmitteln des KIT: „Neuartige Radartechnologien“, gemeinsam mit dem IHE, Prof. Zwick, Laufzeit 2009
  • Erfolgreiche Beantragung eines Start-Up Budget aus den Exzellenzmitteln des KIT: „Virtualisierung heterogener Hardwarearchitekturen“, Laufzeit: Jan-Dez. 2010
  • Beteiligung an der erfolgreichen Beantragung eines Start-Up Budget aus den Exzellenzmitteln des KIT: „Inlinemesstechnik und Sensorik“, gemeinsam mit dem WBK, Prof. Fleischer, Laufzeit Jan.-Dez. 2010

Lehrveranstaltungen

Veröffentlichungen

2017
Access Network Generation for Efficient Debugging of FPGAs

Habib ul Hasan Khan, Tomás Grimm, Michael Hübner, Göhringer, Diana - International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies 2017

Floating-Point Arithmetic using GPGPU on FPGAs

Muhammed Soubhi Al Kadi, Benedikt Janßen, Michael Hübner - IEEE Computer Society Annual Symposium on VLSI, 2017

A CAD Open Platform for high performance reconfigurable systems in the EXTRA project

Rabozzi, Marco, Brondolin, Rolando, Natale, Guiseppe, DelSozzo, Emanuele, Michael Hübner, Brokalakis, Andreas, Ciobanu, Catalin, Stroobandt, Dirk, Santamborgio, Marco - IEEE Computer Society Annual Symposium on VLSI, 2017

Semiformal Verification of Software-controlled Connections

Tomás Grimm, Lettnin, Djones, Michael Hübner

Towards adaptive and efficient bottling plants in a Cyber Physical Production System environment

Florian Kästner, Michael Hübner, Ohrem, Jochen, Cluesserath, Ludwig - 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2017)

A Survey on CNN and RNN Implementations

Javier Hoffmann, Osvaldo Navarro, Florian Kästner, Benedikt Janßen, Michael Hübner - PESARO 2017, The Seventh International Conference on Performance, Safety and Robustness in Complex Systems and Applications

System-level design space identification for many-core vision processors

Jones Yudi Mori Alves da Silva, Carlos Llanos, Michael Hübner - Elsevier Journal on Microcprocessors and Microsystems https://doi.org/10.1016/j.micpro.2017.05.013

An Open Reconfigurable Research Platform as Stepping Stone to Exascale High-Performance Computing

Stroobandt, Dirk, Catalin Bogdan Ciobanu, Marco D. Santambrogio, Jose Gabriel Coutinho, Andreas Brokalakis, Dionisios Pnevmatikatos, Michael Hübner, Tobias Becker, Alex J. W. Thom - Design, Automation and Test in Europe, Lausanne, 2017

Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications

Kulkarni, A., André Werner, Florian Fricke, Stroobandt, D., Michael Hübner - 3rd International Workshop on Overlay Architectures for FPGAs (OLAF2017), Monterey, CA, USA

A Machine Learning Methodology for Cache Recommendation

Osvaldo Navarro, Javier Hoffmann, Fabian Stuckmann, Michael Hübner, Jones Yudi Mori Alves da Silva - 13th International Symposium on Applied Reconfigurable Computing (ARC2017)

2016
Information Fusion of Conflicting Input Data

Uwe Mönks, Dörksen, Helene, Lohweg, Volker, Michael Hübner - Received: 30 July 2016 / Revised: 30 September 2016 / Accepted: 19 October 2016 / Published: 29 October 2016

Integer Computations with Soft GPGPU on FPGAs

Muhammed Soubhi Al Kadi, Michael Hübner - 2016 International Conference on Field-Programmable Technology (FPT '16)

Prozessanlagenplanung 2.0 Netzarchitektur aus Vefahrensbeschreibung ableiten

Thomas Glock, Matthias Kern, Stefan Otten, Eric Sax, Martin Hillenbrand, Michael Hübner - atp edition, vol. 58, no. 10, pp. 28-39, 2016

Automatic Generation of RTL Connectivity Checkers for Automotive Gateways from SystemC TLM Models

Tomás Grimm, Lettnin, Djones, Michael Hübner - IEEE Nordic Circuits and Systems Conference 2017

FPGA Design of Numerical Methods for the Robotic Motion Control Task exploiting High-Level Synthesis

Fynn Schwiegelshohn, Florian Kästner, Michael Hübner - 2016 ICSEE International Conference on the Science of Electrical Engineering- EILAT Israel

Redesign of an Educational Robot Platform Using Web-based Programming

André Werner, Florian Fricke, Benedikt Janßen, Clemens Ribbe, Cengizhan Inac, Michael Hübner - Workshop on Embedded and Cyber-Physical Systems Education

Development of Advanced Driver Assistance Systems using LabVIEW and a Car Simulator

Benedikt Janßen, Philipp Wehner, Diana Göhringer, Michael Hübner - In Proc. of the 12th Workshop on Embedded and Cyber-Physical Systems Education (WESE 2016) at ESWeek, Pittsburgh, PA, USA, 2016.

Multi-level parallelism analysis and system-level simulation for many-core vision processor design

Jones Yudi Mori Alves da Silva, Michael Hübner - 2016 5th Mediterranean Conference on Embedded Computing (MECO)

Smarte Sensoren in der Feldebene

Thomas Glock, Martin Hillenbrand, Michael Hübner - atp edition, vol. 57, no. 11, pp. 32-42, 2015

A Resampling Method for Parallel Filter Architectures

Fynn Schwiegelshohn, Eugen Ossovski, Michael Hübner - Microprocessors and Microsystems, MICPRO2438, 10.1016/j.micpro.2016.07.017, August 2016

Enabling Indoor Object Localization through Bluetooth Beacons on the RADIO Robot Platform

Fynn Schwiegelshohn, Philipp Wehner, Florian Werner, Diana Göhringer, Michael Hübner - In Proc. of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XV), pp. 1-6, Samos, Greece, 2016.

AutoReloc: Automated design flow for bitstream relocation on Xilinx FPGAs

André Lalevée, Pierre-Henri Horrein, Matthieu Arzel, Michael Hübner, Sandrine Vaton - Euromicro Conference on Digital System Design (DSD), 2016, Cyprus

EXTRA: Towards the Exploitation of eXascale Technology for Reconfigurable Architectures

Dirk Stroobandt, Muhammed Soubhi Al Kadi, Michael Hübner - 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), Tallin, Estonia

A framework to the design and programming of many-core focal-plane vision processors

Jones Yudi Mori Alves da Silva, Carlos Llanos, Michael Hübner - 2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing (EUC)

Computation and Communication Challenges to Deploy Robots in Assisted Living Environments

Georgios Keramidas, Christos Antonopoulos, Nikolaos S. Voros, Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Göhringer, Michael Hübner, Stasinos Konstantopoulos, Theodore Giannakopoulos, Vangelis Karkaletsis, Vaggelis Mariatos - In Proc. of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016.

A Design Methodology for the Next Generation Real-Time Vision Processors

Jones Yudi Mori Alves da Silva, André Werner, Arij Shallufa, Florian Fricke, Michael Hübner - International Symposium on Applied Reconfigurable Computing, ARC 2016, Rio de Janeiro, Brazil

A rapid prototyping method to reduce the design time in commercial high-level synthesis tools

Jones Yudi Mori Alves da Silva, André Werner, Florian Fricke, Michael Hübner - 23rd Reconfigurable Architectures Workshop (RAW 2016), Chicago, USA

Efficient Camera Input System and Memory Partition for a Vision Soft-Processor

Jones Yudi Mori Alves da Silva, Frederik Kautz, Michael Hübner - International Symposium on Applied Reconfigurable Computing, ARC 2016, Rio de Janeiro, Brazil

Enabling Dynamic Reconfiguration of Numerical Methods for the Robotic Motion Control Task

Fynn Schwiegelshohn, Florian Kästner, Michael Hübner - 23rd Reconfigurable Architectures Workshop (RAW 2016), Chicago, USA

Hardware/Software Co-Design Approach for Control Applications with Static Real-Time Reallocation

Benedikt Janßen, Moataz Naserddin, Michael Hübner - 23rd Reconfigurable Architectures Workshop (RAW 2016), Chicago, USA

FGPU: An SIMT-Architecture for FPGAs

Muhammed Soubhi Al Kadi, Benedikt Janßen, Michael Hübner - 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016, Monterey, California, February 21 - 23, 2016

2015
Scalable Modular Hardware Platform for FPGA Based Industrial Radar Flowmeters

Timo Jaeschke, P. Imberg, M. Zapke, Michael Hübner, Nils Pohl - in Proc. 2015 International Conference on ReConFigurable Computing and FPGAs, Mayan Riviera, Mexico, Dec. 7-9, 2015

Reconfigurable Processors and Multicore Architectures

Fynn Schwiegelshohn, Philipp Wehner, Jones Yudi Mori Alves da Silva, Benedikt Janßen, Osvaldo Navarro, Jens Rettkowski, Muhammed Soubhi Al Kadi, Diana Göhringer, Michael Hübner - In Reconfigurable Logic: Architecture, Tools, and Applications, CRC Press.

A Holistic Approach for Advancing Robots in Ambient Assisted Living Environments

Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Göhringer, Michael Hübner, Georgios Keramidas, Christos Antonopoulos, Nikolaos S. Voros - In Proc. of the 18th IEEE International Conference on Computational Science and Engineering (CSE 2015), Porto, Portugal, Oct. 2015.

Precise Navigation of Small Agricultural Robots in Sensitive Areas with a Smart Plant Camera

Dworak, Volker, Michael Hübner, Selbeck, Jörn - Journal of Imaging 2015, 1, 115-133, http://www.mdpi.com/2313-433X/1/1/115

The value of FPGAs as reconfigurable hardware enabling Cyber-Physical Systems

Tomás Grimm, Benedikt Janßen, Osvaldo Navarro, Michael Hübner - IEEE 20th Conference on Emerging Technologies & Factory Au­to­ma­ti­on, ETFA 2015, Lu­xem­bourg, Sep­tem­ber 8 to 11, 2015

ViPES 2015 - Preface

Diana Göhringer, Michael Hübner, Jerónimo Castrillón, Cristina Silvano - In Proc. of the 3rd Work­shop on Vir­tu­al Pro­to­typ­ing of Par­al­lel and Em­bed­ded Sys­tems (ViPES)as part of the In­ter­na­tio­nal Con­fe­rence on Em­bed­ded Com­pu­ter Sys­tems: Ar­chi­tec­tu­res, Mo­de­ling, and Si­mu­la­ti­on (SAMOS XV), Samos, Greece, July 2015.

Designing Applications for Heterogeneous Many-Core Architectures with the FlexTiles Platform

Benedikt Janßen, Fynn Schwiegelshohn, Michael Hübner - Embedded Computer Systems (SAMOS), 2015 International Conference on

Configurable Cache Tuning with a Victim Cache

Osvaldo Navarro, Michael Hübner - 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), 29.6. - 1.7.2015, Bremen - Germany

FPGA Based Traffic Sign Detection for Automotive Camera Systems

Fynn Schwiegelshohn, Michael Hübner - 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015), 29.6. - 1.7.2015, Bremen - Germany

Reconfigurable Hardware Enabling Cyber-Physical Systems

Benedikt Janßen, Osvaldo Navarro, Michael Hübner - IEEE 20th International Conference on Emerging Technology & Factory Automation, ETFA 2015, Luxembourg, September 8 to 11, 2015

DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications

Nele Mentens, Jochen Vandorpe, Jo Vliegen, An Braeken, Bruno Da Silva, Abdellah Touhafi, Stephan Knappmann, Alois Kern, Jens Rettkowski, Muhammed Soubhi Al Kadi, Diana Göhringer, Michael Hübner - In Proc. of the 11th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Bochum, Germany, April 2015.

Robots in assisted living environments as an unobtrusive, efficient, reliable and modular solution for independent ageing: The RADIO perspective

Christos Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner, Diana Göhringer, Maria Dagioglou, Theodore Giannakopoulos, Stasinos Konstantopoulos, Vangelis Karkaletsis - In Proc. of the 11th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Bochum, Germany, April 2015.

Adaptive Computing in Real-Time Applications

Benedikt Janßen, Fynn Schwiegelshohn, Michael Hübner - 13th IEEE International NEW Circuits And Systems (NEWCAS) conference, Grenoble, France

A Fully Parallel Particle Filter Architecture for FPGAs

Fynn Schwiegelshohn, Michael Hübner - 11th International Symposium on Applied Reconfigurable Computing, 13 - 17 April 2015

2014
Development of Driver Assistance Systems using virtual Hardware-in-the-Loop

Philipp Wehner, Fynn Schwiegelshohn, Diana Göhringer, Michael Hübner - In Proc. of the International Symposium on Integrated Circuits (ISIC), Singapore, Dec. 2014.

A high-level analysis of a multi-core vision processor using SystemC and TLM2.0

Jones Yudi Mori Alves da Silva, Michael Hübner - 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), December 8-10, 2014, Cancun, Mexico

An Adaptive Victim Cache Scheme

Osvaldo Navarro, Michael Hübner - 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), December 8-10, 2014, Cancun, Mexico

An AXI Compatible Cypress EZ-USB FX3 Interface for USB-3.0 SuperSpeed

Benedikt Janßen, Timo Jaeschke, Michael Hübner - 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), December 8-10, 2014, Cancun, Mexico

An FPGA-Based Implementation of the Schur Method to Compute the Square Root of a Matrix

Janier Arias-Garcia, Michael Hübner, Ricardo Jacobi, Mauricio Ayala-Rincon, Carlos Llanos - 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), December 8-10, 2014, Cancun, Mexico

Considering reconfiguration overhead in scheduling of dependent tasks on 2D Reconfigurable FPGA

Quang-Hai Khuat, Daniel Chillet, Michael Hübner - 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2014)

Design of an Attention Detection System on the Zynq-7000 SoC

Fynn Schwiegelshohn, Michael Hübner - 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), December 8-10, 2014, Cancun, Mexico

Dynamic Run-time Hardware/Software Scheduling For 3D Reconfigurable SoC

Quang-Hai Khuat, Daniel Chillet, Michael Hübner - 2014 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), December 8-10, 2014, Cancun, Mexico

Future Trends on Adaptive Processing Systems

Benedikt Janßen, Jones Yudi Mori Alves da Silva, Osvaldo Navarro, Diana Göhringer, Michael Hübner - In Proc. of the 12th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2014), Milan, Italy, 2014.

A Multi-FPGA Reconfigurable System for accelerating Matlab Simulations

Muhammed Soubhi Al Kadi, Max Ferger, Volker Stegemann, Michael Hübner - 24th International Conference on Field Programmable Logic and Applications Munich, Germany; September 2 - 4, 2014

Considering reconfiguration overhead in scheduling of dependent tasks on 2D Reconfigurable FPGA

Hai Khuat, Daniel Chillet, Michael Hübner - 2014 NASA/ESA Conference on Adaptive Hardware and Systems, Leicester, UK

An Application Scenario for Dynamically Reconfigurable FPGAs

Fynn Schwiegelshohn, Michael Hübner - 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2014), 26 - 28 May 2014, Montpellier - France

OFDM/WDM PON with laserless, colorless 1 Gb/s ONUs based on Si-PIC and slow IC

Agmon, A., Nazarathy, M., Marom, D.M., Ben-Ezra, S., Tolmachev, A., Killey, R., Bayvel, P., Meder, L., Michael Hübner, Meredith, W., Vickers, G., Schindler, P.C., Schmogrow, R., Hillerkuss, D., Freude, W., Koos, C., Leuthold, J. - Optical Communications and Networking, IEEE/OSA Journal of

A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time

Kostas Siozios, Dimitrios Soudris, Michael Hübner - 21st Reconfigurable Architectures Workshop, May 19-20, 2014,Phoenix, USA

Special issue on design and architectures of real-time image processing in embedded systems

Daniel Chillet, Michael Hübner - Journal of Real-Time Image Processing March 2014, Volume 9, Issue 1, pp 1-3

A Framework for Supporting Adaptive Fault Tolerant Solutions

Kostas Siozios, Dimitrios Soudris, Michael Hübner - ACM Transactions on Embedded Computing Systems, Special Issue, 2014

Application exploration with FPGA based emultation exploiting dynamic and partial reconfiguration

Fynn Schwiegelshohn, Michael Hübner - 28th IEEE International Parallel & Distributed Processing Symposium May 19-23, 2014, Arizona Grand Resort, PHOENIX (Arizona) USA

Instruction Set Optimization for Application Specific Processors

Max Ferger, Michael Hübner - 10th International Symposium on Applied Reconfigurable Computing, April 2014, Portugal

System-Level Design Methodologies for Telecommunication

Nicolas Sklavos, Michael Hübner, Diana Göhringer, Paris Kitsos - (Eds., 2014), Springer, ISBN 978-3-319-00663-5.

2013
Dynamic and partial reconfiguration of Zynq 7000 under Linux

Muhammed Soubhi Al Kadi, Patrick Rudolph, Diana Göhringer, Michael Hübner - 2013 International Conference on Reconfigurable Computing and FPFA, December 9-11, 2013, Cancun Mexico

Stopping-free dynamic configuration of a multi-ASIP turbo decoder

Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet - 16th Euromicro Conference on Digital System Design (DSD) 2013, Santander, Spain

Rapid Prototyping of a Portable HW/SW Co-Design on the Virtual Zynq Platform using SystemC

Philipp Wehner, Max Ferger, Diana Göhringer, Michael Hübner - In Proc. of the 26th IEEE International Systems-on-Chip Conference (SOCC), Erlangen, Germany, Sept. 2013

JITPR: A framework for supporting fast application's implementation onto FPGAs

Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Sourdris, Michael Hübner, Jürgen Becker - ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012) TRETS Volume 6 Issue 2, July 2013 Article No. 7

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture

Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet - 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip ReCoSoC 2013, Darmstadt, Germany

On Supporting Adaptive Fault Tolerant at Run - Time with Virtual FPGAs

Kostas Siozios, Dimitrios Soudris, Michael Hübner - 1st Virtual Prototyping of Parallel and Embedded Systems (ViPES) Workshop 2013, Boston, USA

Simplify: a Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud

Gabriel Marchesan Almeida, Oliver Longhi, Thomas Bruckschloegl, Michael Hübner, Fabiano Hessel, Jürgen Becker - 1st Virtual Prototyping of Parallel and Embedded Systems (ViPES) Workshop 2013, Boston, USA

2012
Embedded Systems Start-up under Timing Constraints on Modern FPGAs

J. Meyer, J. Noguera, Michael Hübner, R. Stewart, J. Becker - Embedded Systems Design with FPGAs 2013, pp 149-172

Hardware / Software Virtualization for the Reconfigurable Multicore Platform

Max Ferger, Muhammed Soubhi Al Kadi, Michael Hübner, M. Koedam, S. Sina, K. Goosens, G. Marchesan Almeida, J. Rodrigo Azambuja, J. Becker - Invited paper to the 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2012), Paphos, Cyprus

A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware

J. R. Azambuja, S. Pagliarini, M. Altieri, F. L. Kastensmidt, Michael Hübner, J. Becker, G. Foucard, R. Velazco - IEEE Transactions on Nuclear Science, 2012 Band 59, S. 1117-1124

Virtualization of heterogeneous and adaptive multi-core/multi-board systems

O. Oey, S. Werner, O. Oey, Diana Göhringer, A. Stuckert, J. Becker, Michael Hübner - Conference on Design and Architectures for Signal and Image Processing (DASIP), 2012, Karlsruhe, Germany S. 1-2

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach

J. Becker, T. Stripf, O. Oey, Michael Hübner, S. Derrien, D. Menard, O. Sentieys, G. Rauwerda, K. Sunesen, N. Kavvadias, K. Masselos, G. Goulas, P. Alefragis, N. S. Voros, D. Kritharidis, N. Mitas, Diana Göhringer - 15th Euromicro Conference on Digital System Design (DSD), 2012, Cesme, Izmir, Turkey S. 114-121

On Designing Self-Aware Reconfigurable Platforms

K. Siozos, H. Sidiropoulos, D. Diamantopoulos, P. Figuli, D. Soudris, Michael Hübner, J. Becker - Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, Oslo, Norway

Adaptive Processor Architecture

Michael Hübner, Diana Göhringer, C. Tradowsky, J. Henkel - International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII), 2012, Samos, Greece

From Scilab to multicore embedded systems: Algorithms and methodologies

G. Goulas, P. Alefragis, N. S. Voros, C. Valouxis, C. Gogos, N. Kavvadias, G. Dimitroulakos, K. Masselos, Diana Göhringer, S. Derrien, D. Menard, O. Sentieys, Michael Hübner, T. Stripf, O. Oey, J. Becker, G. Rauwerda, K. Sunesen, D. Kritharidis, N. Mitas - International Conference on Embedded Computer Systems (SAMOS), 2012, Samos, Greece S. 268-275

Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures

Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Juergen Becker, Sebastien Pillement, Olivier Sentieys - International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII), 2012, Samos, Greece

Flexible Approach for Compiling Scilab to Reconfigurable Multi-Core Embedded Systems

T. Stripf, O. Oey, T. Bruckschloegl, R. Koenig, J. Becker, G. Rauwerda, K. Sunesen, T. Perschke, Diana Göhringer, Michael Hübner, G. Goulas, P. Alefragis, N. S. Voros, S. Derrien, D. Menard, O. Sentieys, N. Kavvadias, G. Dimitroulakos, K. Masselos, D. Kritharidis, N. Mitas - In Proc. of the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK.

On-chip monitoring for adaptive heterogeneous multicore systems

Diana Göhringer, M. Chemaou, Michael Hübner - In Proc. of the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK.

Quality metrics for optical signals: Eye diagram, Q-factor, OSNR, EVM and BER

W. Freude, R. Schmogrow, B. Nebendahl, M. Winter, A. Josten, D. Hillerkuss, S. König, J. Meyer, M. Dreschmann, Michael Hübner, C. Koos, J. Becker, J. Leuthold - 14th International Conference on Transparent Optical Networks (ICTON), 2012, Coventry, England S. 1-4

Multi-Client Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer and Application Exploration

Diana Göhringer, L. Meder, S. Werner, O. Oey, J. Becker, Michael Hübner - Hindaw International Journal of Reconfigurable Computing, Special Issue: Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2011)

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation

Soudris Sidropolous, Sourdris Siozos, Michael Hübner - Reconfigurable Architecture Workshop, RAW 2012, Shanghai, China Best Paper Award

A Framework for Exploration of Parallel SystemC Simulation on the Single-chip Cloud Computer

C. Roth, S. Reder, O. Sander, Michael Hübner, J. Becker - 5th International ICST Conference on Simulation Tools and Techniques, Desenzano, Italy, 2012

FPGA controlled DDS based frequency sweep generation of high linearity for FMCW radar systems

S. Ayhan, V. Vu-Duy, P. Pahl, S. Scherr, Michael Hübner, J. Becker, T. Zwick - 7th German Microwave Conference (GeMiC), 2012, Ilmenau, Germany

Virtualized On-Chip Distributed Computing for Heterogeneous Reconfigurable Multi-Core Systems

S. Werner, O. Oey, Diana Göhringer, Michael Hübner, J. Becker - Design, Automation and Test in Europe (DATE), Dresden, Germany

150 Gbit/s Real-Time Nyquist Pulse Transmission Over 150 km SSMF Enhanced by DSP with Dynamic Precision

R. Schmogrow, M. Meyer, S. Wolf, B. Nebendahl, D. Hillerkuss, B. Bäuerle, M. Dreschmann, J. Meyer, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Optical Fiber Communication Conference, S. OM2A.6, 2012, Los Angeles, California United States

Virtualized Distributed Computing for Heterogeneous Adaptive Multi-Core Systems

O. Oey, S. Werner, Diana Göhringer, Michael Hübner, J. Becker - In Proc. of the University Booth of the Design, Automation and Test in Europe (DATE), Dresden, Germany.

Time And Frequency Synchronization For Ultra-High Speed OFDM Systems

M. Dreschmann, J. Meyer, Michael Hübner, R. Schmogrow, D. Hillerkuss, J. Becker, J. Leuthold, W. Freude - In International Conference on Computing, Networking and Communications (ICNC), 2012, Maui, Hawaii, USA

Real-time Nyquist pulse generation beyond 100 Gbit/s and its relation to OFDM

R. Schmogrow, M. Winter, M. Meyer, D. Hillerkuss, S. Wolf, B. Bäuerle, A. Ludwig, B. Nebendahl, S. Ben Ezra, J. Meyer, M. Dreschmann, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Optics Express, Band 20, Issue 1, 2012

Error Vector Magnitude as a Performance Measure for Advanced Modulation Formats

R. Schmogrow, B. Nebendahl, M. Winter, A. Josten, D. Hillerkuss, S. König, J. Meyer, M. Dreschmann, Michael Hübner, C. Koos, J. Becker, W. Freude, J. Leuthold - Photonics Technology Letters, IEEE (Volume: 24, Issue: 1)

2011
Multiprocessor System-on-Chip Hardware Design and Tool Integration

Michael Hübner, Jürgen Becker - 1st Edition., Springer 2011, X, 300 p. 100 illus., ISBN 978-1-4419-6459-5

Adaptive Multi-Client Network-on-Chip Memory

Diana Göhringer, L. Meder, Michael Hübner, J. Becker - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2011, Cancun, Mexico. (Best Paper Award)

Dynamic Processor Reconfiguration

Michael Hübner, C. Tradowsky, Diana Göhringer, L. Braun, F. Thoma, J. Henkel, J. Becker - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, Cancun, Mexico

Embedded Systems Start-up under Timing Constraints on Modern FPGAs

J. Meyer, J. Noguera, Michael Hübner, R. Stewart, J. Becker - 21st International Conference on Field Programmable Logic and Applications (FPL), 2011, Chania, Crete, Greece

Error Vector Magnitude as a Performance Measure for Advanced Modulation Formats

R. Schmogrow, B. Nebendahl, M. Winter, A. Josten, D. Hillerkuss, S. König, J. Meyer, M. Dreschmann, Michael Hübner, C. Koos, J. Becker, W. Freude, J. Leuthold - IEEE Photonics Technology Letters, Volume: 24, Issue: 1, P. 61-63

VLSI 2010 Annual Symposium: Selected papers (Lecture Notes in Electrical Engineering)

Nikolaos Voros, Amar Mukherjee, Nicolas Sklavos, Konstantinos Masselos, Michael Hübner - Vol. 105, 1st Edition., Springer 2011, VIII, 331 p., ISBN 978-94-007-1487-8

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration

J. Meyer, Michael Hübner, L. Braun, O. Sander, J. Noguera, R. Stewart, J. Becker - VLSI 2010 Annual Symposium, Band 95, 2011

RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC

Diana Göhringer, S. Werner, Michael Hübner, J. Becker - International Conference on Field Programmable Logic and Applications (FPL), 2011, Chania, Crete, Greece

MORPHEUS: Exploitation of Reconfiguration for Increased Run-time Flexibility and Self-adaptive Capabilities in Future SoCs

A. Grasset, P. Brelet, P. Millet, P. Bonnot, F. Campi, N. Voros, Michael Hübner, M. Kühnle, F. Thoma, W. Putzke-Röming, A. Schneider - Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, Springer 2011 ISBN: 978-1461400608

Reconfigurable Computing: From FPGAs to Hardware/Software Codesign

João M. P. Cardoso, Michael Hübner - 1st Edition., Springer 2011, XV, 296 p. 107 illus., ISBN 978-1-4614-0060-8

REFLECT: Rendering FPGAs to Multi-Core Embedded Computing

J. M. P. Cardoso, P. C. Diniz, Z. Petrov, Michael Hübner, K. Bertels, H. van Someren, F. Gonçalves, J. G. de F. Coutinho, G. Constantinides, B. Olivier, W. Luk, J. Becker, G. Kuzmanov, F. Thoma, L. Braun, M. Kühnle, R. Nane, V. Sima, K. Krátký, J. C. Alves, J. C. Ferreira - Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, Springer 2011 ISBN: 978-1461400608

Implementation of an ultra-high speed 256-point FFT for Xilinx Virtex-6 devices

M. Dreschmann, J. Meyer, Michael Hübner, R. Schmogrow, D. Hillerkuss, J. Becker, J. Leuthold, W. Freude - International Conference on Industrial Informatics (INDIN), 2011, Caparica, Lisbon, Portugal

Reconfigurable MPSoC versus GPU: Performance, power and energy evaluation

Diana Göhringer, M. Birk, Y. Dasse-Tiyo, N. Ruiter, Michael Hübner, J. Becker - 9th IEEE International Conference on Industrial Informatics (INDIN), 2011, Caparica, Lisbon, Portugal

Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip

Diana Göhringer, O. Oey, Michael Hübner, J. Becker - International Conference on Embedded Computer Systems (SAMOS), 2011, Samos, Greece

Power and Performance Optimization through MPI supported Dynamic Voltage and Frequency Scaling

F. Thoma, Michael Hübner, Diana Göhringer, H. Ü. Yilmaz, J. Becker - 3rd Many-core Application Research Community (MARC) Symposium, Ettlingen, Germany

Software-defined optical transmission

W. Freude, R. Schmogrow, B. Nebendahl, D. Hillerkuss, J. Meyer, M. Dreschmann, Michael Hübner, J. Becker, C. Koos, J. Leuthold - 13th International Conference on Transparent Optical Networks (ICTON) 2011, Stockholm, Sweden

Real-time OFDM transmitter beyond 100 Gbit/s

R. Schmogrow, M. Winter, D. Hillerkuss, B. Nebendahl, S. Ben Ezra, J. Meyer, M. Dreschmann, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Optics Express, Vol. 19, Issue 13, pp. 12740-12749 (2011)

Real-Time Nyquist Pulse Modulation Transmitter Generating Rectangular Shaped Spectra of 112 Gbit/s 16QAM Signals

R. Schmogrow, M. Winter, M. Meyer, D. Hillerkuss, B. Nebendahl, J. Meyer, M. Dreschmann, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Signal Processing in Photonic Communications 2011, Toronto Canada

A heterogeneous SoC Architecture with embedded virtual fpga Cores and Runtime core Fusion

P. Figuli, Michael Hübner, R. Girardey, F. Bapp, T. Bruckschlögl, F. Thoma, J. Henkel, J. Becker - NASA/ESA 6th Conference on Adaptive Hardware and Systems (AHS) 2011, San Diego, CA, USA

Run-Time Resource Instantiation for Fault Tolerance in FPGAs

M. Pereira, L. Braun, Michael Hübner, J. Becker, L. Carro - NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2011, San Diego, CA, USA

Exploration of Power-Performance Tradeoffs through Parameterization of FPGA-based Multiprocessor Systems

Diana Göhringer, J. Obie, A. Braga, Michael Hübner, C. Llanos, J. Becker - Hindawi International Journal of Reconfigurable Computing, Special Issue: Selected Papers from the 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip (ReCoSoC2010)

26 Tbit s-1 line-rate super-channel transmission utilizing all-optical fast Fourier transform processing

D. Hillerkuss, R. Schmogrow, T. Schellinger, M. Jordan, M. Winter, G. Huber, T. Vallaitis, R. Bonk, F. Kleinow, F. Frey, M. Röger, S. König, A. Ludwig, A. Marculescu, J. Li, M. Hoh, M. Dreschmann, J. Meyer, S. Ben Ezra, N. Narkiss, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, A. Öhler, K. Weingarten, T. Ellermeyer, J. Lutz, M. Möller, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Nature Photonics 5 (2011) S.364–371

All-optical real-time OFDM transmitter and receiver

W. Freude, D. Hillerkuss, T. Schellinger, R. Schmogrow, M. Winter, T. Vallaitis, R. Bonk, A. Marculescu, J. Li, M. Dreschmann, J. Meyer, S. Ben Ezra, M. Caspi, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, A. Öhler, K. Weingarten, T. Ellermeyer, J. Lutz, M. Moller, Michael Hübner, J. Becker, C. Koos, J. Leuthold - Conference onLasers and Electro-Optics (CLEO), 2011, Munich, Germany

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture

Michael Hübner, P. Figuli, R. Girardey, D. Soudris, K. Siozos, J. Becker - 18th Reconfigurable Architectures Workshop (RAW), 2011, Anchorage, Alaska, USA

High-Level Design for FPGA-based Multiprocessor Accelerators

Diana Göhringer, M. Birk, Michael Hübner, J. Becker - W2: Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing at the Design, Automation and Test in Europe (DATE)Conference, Grenoble, France.

101.5 Gbit/s Real-Time OFDM Transmitter with 16QAM Modulated Subcarriers

R. Schmogrow, M. Winter, B. Nebendahl, D. Hillerkuss, J. Meyer, M. Dreschmann, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Optical Fiber Communication Conference (OFC) 2011, Los Angeles, CA, United States

Fast Startup for Xilinx FPGAs

J. Meyer, J. Noguera, R. Stewart, Michael Hübner, J. Becker - XCELL Journal Issue 75, 2011

Sequentially configurable programmable integrated circuit

Michael Hübner - Nummer: US000007932743B1 Patent mit Xilinx wurde für den Ross Freeman Award für die innovativsten Erfindungen nominiert

Approach of an FPGA based adaptive stepper motor control system

N. Dahm, Michael Hübner, J. Becker - 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011, Montpellier, France

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

J. Meyer, J. Noguera, Michael Hübner, L. Braun, O. Sander, R. Mateos Gil, R. Stewart, J. Becker - Design, Automation and Test in Europe (DATE) 2011, Grenoble, France

Operating System for Runtime Reconfigurable Multiprocessor Systems

Diana Göhringer, Michael Hübner, E. Nguepi Zeutebouo, J. Becker - Hindawi International Journal of Reconfigurable Computing Special Issue: Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010), 2011

Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT

M. Birk, C. Hagner, M. Balzer, N. Ruiter, Michael Hübner, J. Becker - International Journal of Reconfigurable Computing Special Issue: Selected Papers from the 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip (ReCoSoC2010), 2011

2010
Adaptive Multiprocessor System-on-Chip Architecture – New degrees of freedom in system design and runtime support

Diana Göhringer, Michael Hübner, J.Becker - In: Multiprocessor System-on-Chip: Current Trends and the Future, Springer.

Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems

K. Kepa, F. Morgan, K. Kosciuszkiewicz, L. Braun, Michael Hübner, J. Becker - Transactions on Reconfigurable Technology and Systems (TRETS), 2010

Dynamic System Reconfiguration in Heterogeneous Platforms The MORPHEUS Approach

Nikolaos Voros, Alberto Rosti, Michael Hübner - Series: Lecture Notes in Electrical Engineering Vol. 40, 1st ed. 2009, Springer 2009, XXIV, 280 p. ISBN 978-90-481-2426-8

Performance, Accuracy, Power Consumption and Resource Utilization Analysis for Hardware / Software realized Artificial Neural Networks

A. L. S. Braga, Diana Göhringer, C. H. Llanos, J. Obie, Michael Hübner, J. Becker - International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA), Liverpool, UK.

Debugging Sequential Logic on FPGAs using Internal Configuration Access Port

T. Schwalb, L. Braun, S. Werner, Michael Hübner, K. D. Mueller-Glaser, J. Becker - System, Software, SoC and Silicon Debug Conference (S4D), Southampton, UK, 2010

Real-Time Software-Defined Multi Format Transmitter Generating 64QAM at 28 GBd

R. Schmogrow, D. Hillerkuss, M. Dreschmann, Michael Hübner, M. Winter, J. Meyer, B. Nebendahl, C. Koos, J. Becker, W. Freude, J. Leuthold - Photonics Technology Letters, IEEE (2010: Volume:22, Issue: 21)

All-Optical FTT Signal Processing of a 10.8 Tb/s Single Channel OFDM Signal

J. Leuthold, M. Winter, W. Freude, C. Koos, D. Hillerkuss, T. Schellinger, R. Schmogrow, T. Vallaitis, R. Bonk, A. Marculescu, J. Li, M. Dreschmann, J. Meyer, Michael Hübner, J. Becker, S. Ben Ezra, N. Narkiss, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, A. Oehler, K. Weingarten, T. Ellermeyer, J. Lutz, M. Möller - Photonics in Switching, Monterey, CA, USA, 2010

Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC

Diana Göhringer, Michael Hübner, L. Hugot-Derville, J. Becker - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS X), Samos, Greece

Fast Sequential FPGA Startup based on Partial and Dynamic Reconfiguration

Michael Hübner, J. Meyer, O. Sander, L. Braun, J. Becker, J. Noguera, R. Stewart - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI 2010), Lixouri, Greece, 2010

Reliability Analysis and Improvement in Nano Scale Design

M. Niknahad, Michael Hübner, J. Becker - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), Lixouri Kefalonia, Greece, 2010

Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications

R. Girardey, Michael Hübner, J. Becker - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI), Lixouri, Greece, 2010

First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography

M. Birk, C. Hagner, M. Balzer, N. Ruiter, Michael Hübner, J. Becker - 5th International Workshop on Reconfigurable Communication-centric Systems on Chip (ReCoSoC), Karlsruhe, Germany, 2010

Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors

Diana Göhringer, J. Obie, Michael Hübner, J. Becker - 5th International Workshop on Reconfigurable Communication Centric Systems-on-Chip (ReCoSoC), Karlsruhe, Germany, 2010

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip

Diana Göhringer, Michael Hübner, M. Benz, J. Becker - 18th International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Charlotte, USA

Optically powered low-energy demarcation device for monitoring FTTx networks

M. Roeger, B. Hiba, M. Hoh, J. Hehmann, T. Pfeiffer, Michael Hübner, J. Becker, J. Leuthold, W. Freude - Conference on Optical Fiber Communication collocated National Fiber Optic Engineers Conference (OFC/NFOEC), San Diego, CA, USA, 2010

Single source optical OFDM transmitter and optical FFT receiver demonstrated at line rates of 5.4 and 10.8 Tbit/s

D. Hillerkuss, T. Schellinger, R. Schmogrow, M. Winter, T. Vallaitis, R. Bonk, A. Marculescu, J. Li, M. Dreschmann, J. Meyer, S. Ben Ezra, N. Narkiss, B. Nebendahl, F. Parmigiani, P. Petropoulos, B. Resan, K. Weingarten, T. Ellermeyer, J. Lutz, M. Moller, Michael Hübner, J. Becker, C. Koos, W. Freude, J. Leuthold - Conference on Optical Fiber Communication collocated National Fiber Optic Engineers Conference (OFC/NFOEC), San Diego, CA, USA, 2010

CAP-OS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures

Diana Göhringer, Michael Hübner, E. Nguepi Zeutebouo, J. Becker - IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW), Atlanta, USA, 2010

Fast dynamic and partial reconfiguration Data Path with low Hardware overhead on Xilinx FPGAs

Michael Hübner, Diana Göhringer, J. Noguera, J. Becker - IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum (IPDPSW), Atlanta, USA 2010

Car-to-X Simulation Environment for comprehensive Design Space Exploration Verification and Test

C. Roth, O. Sander, Michael Hübner, J. Becker - SAE 2010 World Congress & Exhibition, Detroit, Michigan, USA

FPGA-based Embedded Signal Processing for 3D Ultrasound Computer Tomography

M. Birk, S. Koehler, M. Balzer, Michael Hübner, N. Ruiter, J. Becker - 17th IEEE-NPSS Real Time Conference (RT), Lissabon, Portugal, 2010

Semi-Automatic Toolchain for Reconfigurable Multiprocessor Systems-on-Chip: Architecture Development and Application Partitioning

Diana Göhringer, Michael Hübner, M. Benz, J. Becker - In Proc. of the International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, USA.

2009
Selected Papers from ReCoSoc 2008

Michael Hübner, G. Sassatelli, P. Zipf - International Journal of Reconfigurable Computing 2009

Konfigurierbares Feldgerät für die Prozessautomatisierungstechnik

Michael Hübner - Patent mit Endress und Hauser 2009, Nummer: EP000002113067A1

A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing

D. Rossi, F. Campi, M. Kuehnle, Michael Hübner, J. Becker - International Symposium on System-on-Chip, Tampere, Finland, 2009

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip

F. Campi, R. Koenig, M. Dreschmann, M. Neukirchner, D. Picard, M. Juttner, E. Schuler, A. Deledda, D. Rossi, A. Pasini, Michael Hübner, J. Becker, R. Guerrieri - International Symposium on System-on-Chip, Tampere, Finland, 2009

BRICK: a multi-context expression grained reconfigurable architecture

Juan Fernando Eusse, Michael Hübner, R. Jacobi - 22nd Symposium on Integrated Circuits and System, SBCCI, Natal, Brazil, 2009

Dynamic Reconfigurable Mixed-Signal Architecture for Safety Critical Applications

R. Girardey, Michael Hübner, J. Becker - 19th International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, 2009

Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit- and a packet-switching communication protocol

Diana Göhringer, B. Liu, Michael Hübner, J. Becker - 19th International Conference on Field Programmable Logic and Applications (FPL), Prague, Czech Republic, 2009

System zur flexiblen Konfiguration von Funktionsmodulen

Michael Hübner - Patent mit Endress und Hauser 2009, Nummer: EP000002082485A2

A Taxonomy of Reconfigurable Single/Multi-Processor Systems-on-Chip

Diana Göhringer, Michael Hübner, T. Perschke, J. Becker - Hindawi International Journal of Reconfigurable Computing.

Routingmodul zum Datenaustausch

Michael Hübner - Patent mit Daimler 2009, Nummer: DE102007049043A1

2008
Current Trends on Reconfigurable Computing

J. Becker, Michael Hübner, R. Woods, P. Long, R. Esser, L. Torres - International Journal of Reconfigurable Computing, 2008

Adaptive real time image processing exploiting two dimensional reconfigurable architecture

L. Braun, Diana Göhringer, T. Perschke, V. Schatz, Michael Hübner, J. Becker - Springer Journal of Real-Time Image Processing, vol. 4, no. 2, pp.109-125.

Standards for Electric/Electronic Components and Architectures

J. Becker, O. Sander, Michael Hübner, M. Traub, T. Weber, J. Luka, V. Lauer - Convergence 2008, Detroit, USA

An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC

M. Kuehnle, Michael Hübner, J. Becker, A. Deledda, C. Mucci, F. Ries, A. M. Coppola, L. Pieralisi, R. Locatelli, G. Maruccia, T. DeMarco, F. Campi - IEEE Design & Test of Computers 2008

Dynamic Reconfiguration of Nano Architectures using Application Independent Fault Detection

M. Niknahad, C. Schuck, Michael Hübner, J. Becker - AMWAS School and Workshop, Lugano, Switzerland, 2008

Techniques for Power Optimized FPGA Design: Novel Approaches towards Power Reduction for Future Tool Supported Design Automation

R. Esser, J. Noguera, J. Becker, Michael Hübner, K. Paulsson - PATMOS 2008, Lisbon Portugal

A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput

C. Claus, B. Zhang, W. Stechele, L. Braun, Michael Hübner, J. Becker - International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, 2008

Data path driven waveform-like reconfiguration

L. Braun, K. Paulsson, H. Kromer, Michael Hübner, J. Becker - International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, 2008

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization

K. Paulsson, Michael Hübner, J. Becker - Field Programmable Logic and Applications (FPL), Heidelberg, Germany, 2008

Fine grain reconfigurable architectures

J. Angermeier, M. Majer, J. Teich, L. Braun, T. Schwalb, P. Graf, Michael Hübner, J. Becker, E. Lubbers, M. Platzner, C. Claus, W. Stechele, A. Herkersdorf, M. Rullmann, R. Merker - International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, 2008

New Dimensions for Multiprocessor Architectures: On Demand Heterogeneity, Infrastructure and Performance through Reconfigurability: The RAMPSoC Approach

Diana Göhringer, Michael Hübner, T. Perschke, J. Becker - International Conference on Field Programmable Logic and Applications (FPL), Heidelberg, Germany, 2008

Data Reallocation by Exploiting FPGA Configuration Mechanism

O. Sander, L. Braun, Michael Hübner, J. Becker - Reconfigurable Computing: Architectures, Tools and Applications (RAW), Miami, Florida, USA, 2008

FPGA Based Stepper Motor Control Function Exploiting Run-Time Reconfiguration

N. Dahm, Michael Hübner, J. Becker - ReCoSoC Workshop Proceedings, Barcelona, Spain, 2008

A framework for dynamic 2D placement on FPGAs

C. Schuck, M. Kuehnle, Michael Hübner, J. Becker - IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Miami, Florida, USA

Run-Time Reconfigurable Adaptive Multilayer Network-on-Chip for FPGA-based Systems

Michael Hübner, L. Braun, Diana Göhringer, J. Becker - IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Miami, Florida, USA, 2008

Runtime Adaptive Multi-Processor System-on-Chip: RAMPSoC

Diana Göhringer, Michael Hübner, V. Schatz, J. Becker - IEEE International Symposium on Parallel and Distributed Processing (IPDPS), Miami, Florida, USA.

Cost and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs

K. Paulsson, Michael Hübner, J. Becker - Design, Automation and Test in Europe (DATE), Munich Germany, 2008

Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs

K. Paulsson, U. Vierec, Michael Hübner, J. Becker - Symposium on VLSI (ISVLSI), Montpellier, France, 2008

Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor

A. Deledda, C. Mucci, A. Vitkovski, M. Kuehnle, F. Ries, Michael Hübner, J. Becker, P. Bonnot, A. Grasset, P. Millet, M. Coppola, L. Pieralisi, R. Locatelli, G. Maruccia, F. Campi, T. DeMarco - Design, Automation and Test in Europe (DATE), Munich, Germany, 2008

An Optically Powered Video Camera Link

G. Boettger, M. Dreschmann, C. Klamouris, Michael Hübner, M. Röger, A. W. Bett, T. Kueng, J. Becker, W. Freude, J. Leuthold - IEEE Photonics Technology Letters 2008

2007
Optically Powered Video Camera Link

G. Boettger, Michael Hübner, C. Klamouris, M. Dreschmann, A. W. Bett, J. Becker, W. Freude, J. Leuthold, M. Roeger - 33rd European Conference and Exhibition on Optical Communication (ECOC), Berlin, Germany, 2007

A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures

P. Graf, Michael Hübner, K. D. Mueller-Glaser, J. Becker - International Conference on Field Programmable Logic and Applications, (FPL), Amsterdam, The Netherlands, 2007

Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications

L. Braun, Michael Hübner, J. Becker, T. Perschke, V. Schatz, S. Bach - International Conference on Field Programmable Logic and Applications, (FPL), Amsterdam, The Netherlands, 2007

Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs

K. Paulsson, Michael Hübner, G. Auer, M. Dreschmann, L. Chen, J. Becker - International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, The Netherlands, 2007

On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the AETHER Project

K. Paulsson, Michael Hübner, J. Becker, J.-M. Philippe, C. Gamrat - International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, The Netherlands, 2007

Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems

K. Paulsson, Michael Hübner, S. Bayar, J. Becker - ReCoSoc, Montpellier, France, 2007

Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC

V. Brito, M. Kuehnle, Michael Hübner, J. Becker, E. U. K. Melcher - International Symposium on VLSI, Porto Alegre, Brazil, 2007

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs

Michael Hübner, L. Braun, J. Becker, C. Claus, W. Stechele - IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Porto Alegre, Brazil, 2007

Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs

Michael Hübner, L. Braun, J. Becker - IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Porto Alegre, Brazil, 2007

Communication Architectures for Dynamically Reconfigurable FPGA Designs

T. Pionteck, C. Albrecht, R. Koch, E. Maehle, Michael Hübner, J. Becker - Parallel and Distributed Processing Symposium IPDPS, Long Beach, CA, USA, 2007

Dynamic and Partial FPGA Exploitation

J. Becker, Michael Hübner, G. Hettich, R. Constapel, J. Eisenmann, J. Luka - IEEE Special Issue "Advanced Automobile Technologies" (February 2007, Volume 95, Number 2

2006
Optically Powered Video Camera Network

G. Boettger, Michael Hübner, M. Dreschmann, C. Klamouris, K. Paulsson, T. Kueng, A. W. Bett, J. Becker, W. Freude, J. Leuthold - VDE-ITG-Fachtagung Kommunikationskabelnetze, Cologne, Germany, 2006

Optically powered platform with Mb/s transmission over a single fiber

C. Klamouris, G. Boettger, Michael Hübner, M. Dreschmann, K. Paulsson, A. W. Bett, T. Kueng, J. Becker, W. Freude, J. Leuthold - 32th European Conf. Optical Communications (ECOC), Cannes, France, 2006

Vorrichtung und Verfahren zur Abarbeitung priorisierter Steuerungsprozesse

Michael Hübner - Patent mit Daimler 2006, Nummer: DE102005010477A1

Exploiting Dynamic and Partial Reconfiguration for FPGAs - Toolflow, Architecture and System Integration

Michael Hübner, J. Becker - Invited Tutorial, SBCCI, Ouro Preto, Brazil, 2006

On-Line Optimization of FPGA Power-Dissipation by Exploiting Run-time Adaption of Communication Primitives

K. Paulsson, Michael Hübner, J. Becker - SBCCI, Ouro Preto, Brazil, 2006

Run-time Reconfigurabilility and other Future Trends

J. Becker, Michael Hübner - SBCCI, Ouro Preto, Brazil, 2006

Steuergerät mit konfigurierbaren Hardwaremodulen

Michael Hübner - Patent mit Daimler 2006 Nummer: DE102005010476A1

Strategies to On-Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration

K. Paulsson, Michael Hübner, J. Becker - Adaptive Hardware and Systems (AHS), Istanbul, Turkey, 2006

Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs

Michael Hübner, C. Schuck, J. Becker - 20th International Parallel and Distributed Processing Symposium (IPDPS) 2006, Rhodos, Greece

Physical 2D Morphware and Power Reduction Methods for Everyone

J. Becker, Michael Hübner, K. Paulsson - Dagstuhl Seminar, Schloss Dagstuhl, Germany, 2006

Seamless Design Flow for Run-Time Reconfigurable Automotive Systems

Michael Hübner, J. Becker - Date 2006, Automotive Friday Workshop, Munich, Germany

New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

Michael Hübner, C. Schuck, M. Kuehnle, J. Becker - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2006, Karlsruhe, Germany

Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs

K. Paulsson, Michael Hübner, M. Jung, J. Becker - International Symposium on VLSI 2006, Karlsruhe, Germany

Tutorial on Macro Design for Dynamic and Partially Reconfigurable Systems

Michael Hübner, J. Becker - RC-Education 2006, Karlsruhe, Germany

2005
Models and Tools for the Dynamic Reconfiguration of FPGAs

A. Donlin, J. Becker, Michael Hübner - IEEE-SOCC, Washington, USA, 2005

Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics

J. Becker, Michael Hübner, K. Paulsson, A. Thomas - ReCoSoc, Montpellier, France, 2005

Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores

Michael Hübner, K. Paulsson, J. Becker - Parallel and Distributed Processing Symposium (IPDPS) 2005, Denver, USA

Automotive Control Unit Optimisation Perspectives: Body Functions on-Demand by Dynamic Reconfiguration

J. Becker, Michael Hübner, K. D. Mueller-Glaser, R. Constapel, J. Luka, J. Eisenmann - DATE, Munich, Germany, 2005

Real-time configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation

Michael Hübner, M. Ullmann, J. Becker - International Journal Embedded Systems Vol. 1, No. 3/4, 2005, pp. 263 - 273

2004
Real-time LUT-based Network Topologies for dynamic and partial FPGA Self-Reconfiguration

Michael Hübner, T. Becker, J. Becker - SBCCI, Porto de Galinhas, Brazil, 2004

Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems

Michael Hübner, M. Ullmann, L. Braun, A. Klausmann, J. Becker - Field Programmable Logic and Application Lecture Notes in Computer Science Volume 3203, 2004, pp 1037-1041

On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities

M. Ullmann, Michael Hübner, B. Grimm, J. Becker - FPL, Antwerpen, Belgien, 2004

Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs

B. Blodget, C. Bobda, Michael Hübner, A. Niyonkuru - Tutorial Paper, FPL, Antwerpen, Belgien, 2004

An FPGA Run-Time System for Dynamical On-Demand Reconfiguration

M. Ullmann, B. Grimm, Michael Hübner, J. Becker - IPDPS 2004, Santa Fe, USA

Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration

Michael Hübner, M. Ullmann, F. Weissel, J. Becker - IPDPS 2004, Santa Fe, USA

2003
Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations

J. Becker, Michael Hübner, M. Ullmann - VLSI-Soc, Darmstadt, Germany, 2003

Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations

J. Becker, Michael Hübner, M. Ullmann - 16th Symposium on Integrated Circuits and Systems Design (SBCCI), Sao Paulo, Brazil, 2003