course: Master Project Virtual Prototyping of Embedded Systems

number:
142184
teaching methods:
project
responsible person:
Prof. Dr.-Ing. Michael Hübner
lecturers:
Prof. Dr.-Ing. Michael Hübner (ETIT), Benedikt Janßen (ETIT), M. Sc. Jones Yudi Mori Alves da Silva (ETIT), M. Sc. Osvaldo Navarro (ETIT)
language:
english
HWS:
3
CP:
3
offered in:
winter term

dates in winter term

  • kick-off meeting: Wednesday the 11.10.2017 from 16:15 in ID 1/103
  • lab Mondays: from 09:00 to 12.00 o'clock in ID 1/103

Exam

Project

continual assessment

goals

The students master the design of “Embedded Systems” with the help of “Virtual Prototyping”. Besides using tools for modeling, simulation and analysis of a virtual “Embedded System”, the students will also be able to use SystemC, a hardware description language based on C++, and to model selected peripheral components. Furthermore they can implement applications in connection with the designed processor platform and a real-time operating system.

content

Within the project's scope, the methods of “Virtual Prototyping” are taught and reinforced with practical examples. The course's agenda is described below:

  1. Introduction to Virtual Prototyping basic concepts, systems, tools, languages, etc.
  2. SystemC basic course

This course is based on the IEEE SystemC TLM2.0 library, and aims to provide the basic understanding about the SystemC language and the Transaction-Level Modeling (TLM) standard.:

  • Introduction to Transaction-Level Modeling
  • Working with Loosely-Timed models
  • Working with Approximately-Timed models
  • Debugging methods
  1. Tensilica Processor design framework

The objective is to provide hands-on knowledge about the Cadence Xtensa Xplorer framework to design custom processor architectures based on the Xtensa LX series processors:

  • Tensilica Processor Architecture
  • Programming Cores with Tensilica Instruction Extensions
  • Developing Software for Xtensa Processors
  • Xtensa Debug and Trace
  • Support for Emulation
  1. Virtual System Platform

This course uses the Cadence Virtual System Platform to integrate hardware and software platforms using fast processor models. The simulation platforms are based on SystemC/TLM2.0 models and allows for fast hardware emulation and early software development.

  • Tool overview
  • Selected examples
  • Custom models design and analysis
  • Fast processor models integration
  • System-on-Chip ESL design

requirements

none

recommended knowledge

Basic programming knowledge in C/C++

miscellaneous

Registration: as of now with Jones Yudi Mori Alves da Silva, M. Sc., email: Jones.MoriAlvesDaSilva@rub.de, Room: ID 1-336

The number of participants is limited. If the number of registrations exceeds the available capacity, the registrations are dealt with on a “first come, first served” basis.